1. Field of the Invention
This invention relates to integrated circuits and more specifically to input structures in integrated circuits for protecting against damage caused by electrostatic discharge (ESD).
2. Description of the Prior Art
Electrostatic discharge pulses are a well known phenomenon and can be generated by any of a number of causes, e.g., when a person walks across a carpet and touches a grounded metal object. These pulses, which can be several thousand volts, are known to destroy integrated circuits and especially MOS integrated circuits. Such a pulse typically destroys the gate dielectric of MOS devices thereby rendering the devices inoperative. It is known in the art to provide a variety of devices connected to the input pins of MOS integrated circuits to reduce the likelihood of damage caused by electrostatic discharge. An overview of such structures is provided in "Gate Protection of MIS Devices" by Martin Lenzlinger, published in IEEE Transactions on Electronic Devices, Volume FD-18, No. 4 in April 1971.
Lenzlinger discusses the use of a diode as a gate protection device for a P channel MOS transistor as illustrated in FIG. 1a. When the voltage at the gate of a P channel MOS transistor 12 increases negatively, e.g., as the result of an ESD pulse, a diode 14 breaks down so that the voltage present at the gate of transistor 12 is limited to the breakdown voltage of the diode. A positive ESD pulse on input lead 10 forward biases and thus turns on diode 14 thereby protecting the gate of transistor 12. During normal operation, diode 14 is reverse biased and its only effects are an increase in input capacitance and leakage current. In most applications, these effects are negligible. When voltages outside the normal operating range are applied to the gate of transistor 12, diode 14 is either forward biased, in which case it conducts current, or reverse biased, in which case the diode junction breaks down. In this way, diode 14 provides a current path to prevent the voltage at the gate of transistor 12 from rising to a point sufficient to break down the gate isolation layer. If transistor 12 is an N channel device, positive input voltages would be applied to lead 10 and the orientation of diode 14 would be reversed.
It is known in the art, when fabricating a diode such as diode 14, to increase its perimeter. This is because when a diode breaks down, most of the energy is dissipated along the periphery of the diode because of the well known field curvature phenomenon. This phenomenon is discussed on pages 106-108 of Physics of Semiconductor Devices by S. M. Sze, published by Wiley in 1981.
A variation of the circuit in FIG. la is provided in FIG. lb in which a series resistor RS is provided between input lead 10 and the gate of transistor 12. In addition, a resistor RD is illustrated in FIG. lb indicative of the inherent resistance in diode 14. Resistor RS and RD form a voltage divider network which further limits the voltage present at the gate of transistor 12. Still another variation of the input protection circuit is illustrated in FIG. lc. Referring to FIG. lc instead of providing a single resistor RS and a single diode 14, a resistor RS' is provided which can be modeled as a distributed resistor diode network as indicated in Fig. 1c. An analysis of this network is provided in the above-mentioned Lenzlinger article. Unfortunately, none of these circuits are completely effective in preventing damage due to ESD pulses, predominantly for the following reasons. First, during the breakdown mode, the voltage at the gate of transistor 12 is increased by the voltage drop across diode resistance RD. To ensuring sufficient protection requires a very large diode (in order to reduce resistance RD) which is impractical for VLSI circuits. Second, any increase in series input resistance RS increases the RC time delay associated with these circuits.
Another prior art circuit for protecting the gate of an MOS transistor is illustrated in FIG. ld. Referring to FIG. ld, an NPN bipolar transistor 16 is connected between the gate of N channel MOS transistor 12 and ground. When a large voltage is applied to input lead 10, transistor 16 breaks down, thus protecting transistor 12. Various geometries for transistor 16 of FIG. ld are discussed in U.S. Pat. No. 3,787,717 issued to Fischer, et al. and U.S. Pat. No. 4,080,616 issued to Nobory Horie. However, these structures are also not completely effective in preventing damage due to ESD pulses.